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nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 1 advance information 512k x 32 module nvsram 3.3v high speed sram with non-volatile storage available as military specifications ? military processing (mil-std-883c para 1.2.2) ? temperature range -55c to 125c features ? -55 o c to 125 o c operation ? true non-volatile sram (no batteries) ? 20 ns, 25 ns, and 45 ns access times ? automatic store on power down with only a small capacitor ? store to quantumtrap ? nonvolatile elements initiated by software, device pin, or autostore ? on power down ? recall to sram initiated by software or power up ? in nite read, write, and recall cycles ? 200,000 store cycles to quantumtrap ? 20 year data retention ? single 3.3v +/- 0.3v operation ? ceramic hermetic 68 quad flat pack -matches compatible pinout footprint of sram & eeprom module functional description the as8nvlc512k32 is a fast static ram, with a nonvolatile element in each memory cell. the memory is organized as 512k bytes of 8 bits for each of 4 die to form 512kx32. the embedded nonvolatile elements incorporate quantumtrap technology, producing the world?s most reliable nonvolatile memory. the sram provides in nite read and write cycles, while independent nonvolatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. options marking ? 68 ceramic quad flat pack q 68 ceramic quad flat pack qb ? timing (cycle time) 45ns -45 25ns -25 20ns -20 ? operating temperature ranges -industrial temp (-40c to 85 c) it -enhanced temp (-40c to 105 c) et -military temp (-55c to 125c) xt -military processing (-55c to 125c) mil pin assignment (top view) 68 lead cqfp (q) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 gnd i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 vcc a11 a12 a13 a14 a15 a16 ce1\ oe\ ce2\ a17 we2\ we3\ we4\ a18 nc hsb\ vcap a0 a1 a2 a3 a4 a5 ce3\ gnd ce4\ we1\ a6 a7 a8 a9 a10 vcc 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 pinout / block diagram ce ce ce ce m1 m2 m3 m4 vcap hsb 1 notes: 1. hsb\ signal is wired to all 4 die in module. this can be left open if not used.
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 2 advance information logic block diagram 67$7,&5$0 $55$< ; 5 2 : ' ( & 2 ' ( 5 &2/801,2 &2/801'(& , 1 3 8 7 % 8 ) ) ( 5 6 32:(5 &21752/ 6725(5(&$// &21752/ 4xdwuxp7uds ; 6725( 5(&$// 9 && 9 &$3 +6% $ $ $ $ $ $ $ $ 62)7:$5( '(7(&7 $ $ 2( &( :( %+( %/( $ $ $ $ $ $ $ $ $ $ $ '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 '4 28 '4 29 '4 30 '4 31 [1, 2, 3] dq0-dq31 4x 4x (1-4) (1-4) pin name i/o type description a0 ? a18 input address inputs used to select one of the 524,288 32 r bit words of the nvsram. dq0 ? dq7 dq0 ? dq15 dq16 r dq23 dq24 r dq31 we\ 1 r 4 input write enable input, active low. when selected low, data on the i/o pins is written to the specific address location. ce\ 1 r 4 input chip enable input, active low. when low, selects the chip. when high, deselects the chip. oe\ input output enable, active low. the active low oe input enables the data output buffers during read cycles. i/o pins are tri r stated on deasserting oe high. v ss ground ground for the device. must be connected to the ground of the system. v cc power supply power supply inputs to the device. hsb\ input/output hardware store busy (hsb\). when low this output indicates that a hardware store is in progress. when pulled low external to the chip it initiates a nonvolatile store operation. a weak internal pull up resistor keeps this pin high if not connected (connection optional). after each store operation hsb\ is driven high for short time with standard output high current. v cap power supply autostore capacitor. supplies power to the nvsram during power loss to store data from sram to nonvolatile elements. nc no connect no connect. this pin is not connected to the die. input/output bidirectional data i/o lines for die m1 (dq0 r 7), m2 (dq8 r 15), m3 (dq16 r 23), m4 (dq 24 r 31)
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 3 advance information device operation the as8nvlc512k32 nvsram is made up of two functional components paired in the same physical cell. they are a sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferred to the nonvolatile cell (the store operation), or from the nonvolatile cell to the sram (the recall operation). using this unique architecture, all cells are stored and recalled in parallel. during the store and recall operations, sram read and write operations are inhibited. the as8nvlc512k32 supports in nite reads and writes similar to a typical sram. in addition, it provides in nite recall operations from the nonvolatile cells and up to 200k store operations. see the truth table for sram operations for a complete description of read and write modes. sram read the as8nvlc512k32 performs a read cycle when ce\ and oe\ are low and we\ and hsb\ are high. the address speci ed on pins a0-18 determines which of the 524,288 data bytes. when the read is initiated by an address transition, the outputs are valid after a delay of t aa (read cycle 1). if the read is initiated by ce\ or oe\, the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data output repeatedly responds to address changes within the t aa access time without the need for transitions on any control input pins. this remains valid until another address change or until ce\ or oe\ is brought high, or we\ or hsb\ is brought low. sram write a write cycle is performed when ce\ and we\ are low and hsb\ is high. the address inputs must be stable before entering the write cycle and must remain stable until ce\ or we\ goes high at the end of the cycle. the data on the common i/o pins dq0?31 are written into the memory if the data is valid t sd before the end of a we\ controlled write or before the end of an ce\ controlled write. it is recommended that oe\ be kept high during the entire write cycle to avoid data bus contention on common i/o lines. if oe\ is left low, internal circuitry turns off the output buffers thzwe after we\ goes low. autostore operation the as8nvlc512k32 stores data to the nvsram using one of the following three storage operations: hardware store activated by hsb\; software store activated by an address sequence; autostore on device power down. the autostore operation is a unique feature of quantumtrap technology and is enabled by default on the as8nvlc512k32 . during a normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. figure 2 shows the proper connection of the storage capacitor (v cap ) for automatic store operation. refer to dc electrical characteristics for the size of v cap . the voltage on the v cap pin is driven to v cc by a regulator on the chip. a pull up should be placed on we\ to hold it inactive during power up. this pull up is effective only if the we\ signal is tri-state during power up. many mpus tri-state their controls on power up. this should be veri ed when using the pull up. when the nvsram comes out of power-on-recall, the mpu must be active or the we\ held inactive until the mpu comes out of reset. to reduce unnecessary nonvolatile stores, autostore and hardware store operations are ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initiated store cycles are performed regardless of whether a write operation has taken place. the hsb\ signal is monitored by the system to detect if an autostore cycle is in progress. 0.1uf vcc 10kohm v cap vcc we v cap v ss hardware store operation the as8nvlc512k32 provides the hsb\ 6 pin to control and acknowledge the store operations. use the hsb\ pin to request a hardware store cycle. when the hsb pin is driven low, the as8nvlc512k32 conditionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram has taken place since the last store or recall cycle. the hsb\ pin also acts as an open drain driver that is internally driven low to indicate a busy condition when the store (initiated by any means) is in progress. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. after hsb\ goes low, the as8nvlc512k32 continues sram operations for tdelay. if a write is in progress when hsb\ is pulled low it is enabled a time, t delay to complete. however, any sram write cycles requested after hsb\ goes low are inhibited until hsb\ returns high. in case the write latch is not set, hsb\ is not driven low by the as8nvlc512k32. but any sram read and write cycles are inhibited until hsb\ is returned high by mpu or other external source. during any store operation, regardless of how it is initiated, the as8nvlc512k32 continues to drive the hsb\ pin low, releasing it only when the store is complete. when the store operation is completed, the as8nvlc512k32 remains disabled until the hsb\ pin returns high. leave the hsb\ unconnected if it is not used.. figure 2. autostore mode 1-4
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 4 advance information hardware recall (power up) during power up or after any low power condition (vcc< vswitch), an internal recall request is latched. when vcc again exceeds the sense voltage of vswitch, a recall cycle is automatically initiated and takes threcall to complete. during this time, hsb is driven low by the hsb driver. software store transfer data from the sram to the nonvolatile memory with a software address sequence. the as8nvlc512k32 software store cycle is initiated by executing sequential ce controlled read cycles from six speci c address locations in exact order. during the store cycle an erase of the previous nonvolatile data is rst performed, followed by a program of the nonvolatile elements. after a store cycle is initiated, further input and output are disabled until the cycle is completed. because a sequence of reads from speci c addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no store or recall takes place. to initiate the software store cycle, the following read sequence must be performed. 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8fc0 initiate store cycle the software sequence may be clocked with ce controlled reads or oe controlled reads. after the sixth address in the sequence is entered, the store cycle commences and the chip is disabled. hsb is driven low. it is important to use read cycles and not write cycles in the sequence, although it is not necessary that oe be low for a valid sequence. after the tstore cycle time is ful lled, the sram is activated again for the read and write operation. software recall transfer the data from the nonvolatile memory to the sram with a software address sequence. a software recall cycle is initiated with a sequence of read operations in a manner similar to the software store initiation. to initiate the recall cycle, the following sequence of ce controlled read operations must be performed. 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4c63 initiate recall cycle internally, recall is a two step procedure. first, the sram data is cleared; then, the nonvolatile information is transferred into the sram cells. after the trecall cycle time, the sram is again ready for read and write operations. the recall operation does not alter the data in the nonvolatile elements. mode selection notes 7. while there are 19 address lines on the as8nvlc512k32, only the 13 address lines (a 14 - a 2 ) are used to control software modes. rest of the address lines are don?t care. 8. the six consecutive address locations must be in the order listed. we must be high during all six cycles to enable a nonvola tile cycle. 13.we\ must be high during sram read cycles. ce\ 1 r 4 we\ 1 r 4 oe\ 13 a15 r a0 7 mode i/o 0 r 31 power hxxxnot selected output high z standby l h l x read sram output data active llxxwrite sram input data active lhl0x4e38read sram output data active 8 0xb1c7 read sram output data 0x83e0 read sram output data 0x7c1f read sram output data 0x703f read sram output data 0x8b45 autostore output data disable
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 5 advance information mode selection (continued) preventing autostore the autostore function is disabled by initiating an autostore disable sequence. a sequence of read operations is performed in a manner similar to the software store initiation. to initiate the autostore disable sequence, the following sequence of ce controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8b45 autostore disable the autostore is re-enabled by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initiation. to initiate the autostore enable sequence, the following sequence of ce controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4b46 autostore enable if the autostore function is disabled or re-enabled, a manual store operation (hardware or software) must be issued to save the autostore state through subsequent power down cycles. the part comes from the factory with autostore enabled. data protection the as8nvlc512k32 protects data from corruption during low voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when vcc < vswitch. if the as8nvlc512k32 is in a write mode (both ce and we are low) at power up, after a recall or store, the write is inhibited until the sram is enabled after tlzhsb (hsb to output active). this protects against inadvertent writes during power up or brown out conditions. ce\ 1 r 4 we\ 1 r 4 oe\ 13 a15 r a0 7 mode i/o 0 r 31 power lhl0x4e38read sram output data active 8 0xb1c7 read sram output data 0x83e0 read sram output data 0x7c1f read sram output data 0x703f read sram output data 0x4b46 autostore enable output data lhl0x4e38read sram output data active i cc2 8 0xb1c7 read sram output data 0x83e0 read sram output data 0x7c1f read sram output data 0x703f read sram output data 0x8fc0 nonvolatile store output high z lhl0x4e38read sram output data active 8 0xb1c7 read sram output data 0x83e0 read sram output data 0x7c1f read sram output data 0x703f read sram output data 0x4c63 nonvolatile output high z recall
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 6 advance information best practices nvsram products have been used effectively for over 15 years. while ease-of-use is one of the product?s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: the nonvolatile cells in this nvsram product are delivered from micross componenets with 0x00 written in all cells. incoming inspection routines at customer or contract manufacturer?s sites sometimes reprogram these values. final nv patterns are typically repeating patterns of aa, 55, 00, ff, a5, or 5a. end product?s rmware should not assume an nv array is in a set programmed state. routines that check memory content values to determine rst time system con guration, cold or warm boot status, and so on should always program a unique nv pattern (that is, complex 4-byte pattern of 46 e6 49 53 hex or more random bytes) as part of the nal system manufacturing test to ensure these system routines work consistently. power up boot rmware routines should rewrite the nvsram into the desired state (for example, autostore enabled). while the nvsram is shipped in a preset state, best practice is to again rewrite the nvsram into the desired state as a safeguard against events that might ip the bit inadvertently such as program bugs and incoming inspection routines. the v cap value speci ed in this data sheet includes a minimum and a maximum value size. best practice is to meet this requirement and not exceed the maximum v cap value because the nvsram internal algorithm calculates v cap charge and discharge time based on this max v cap value. customers that want to use a larger v cap value to make sure there is extra store charge and store time should discuss their v cap size selection with micross components to understand any impact on the v cap voltage level at the end of a t recall period.
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 7 advance information maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .............................................?65c to +150c maximum accumulated storage time at 150c ambient temperature...............................1000h at 85c ambient temperature.............................20 years ambient temperature with power applied ......................................................?55c to +125c supply voltage on vcc relative to gnd................... ?0.5v to 4.1v voltage applied to outputs in high-z state ............................................... ?0.5v to vcc + 0.5v input voltage .................................................. ?0.5v to vcc + 0.5v transient voltage (<20 ns) on any pin to ground potential............................?2.0v to vcc + 2.0v package power dissipation capability (ta = 25c) ...........................................................1.0w surface mount pb soldering temperature (3 seconds)......................................................+260c dc output current (1 output at a time, 1s duration) ..............15 ma static discharge voltage .................................................... > 2001v (per mil-std-883, method 3015) latch up current............................................................. > 200 ma operating range notes 9. typical conditions for the active current shown on the dc electrical characteristics are average values at 25c (room temper ature), and v cc = 3v. not 100% tested. 10. the hsb\ pin has i out = -8 ua for v oh of 2.4v when both active high and low drivers are disabled. when they are enabled standard v oh and v ol are valid. this parameter is characterized but not tested. dc electrical characteristics over the operating range (v cc = 3.0v to 3.6v) parameter description min max unit military 320 320 260 ma ma ma industrial 280 280 210 ma ma ma i cc2 average v cc current during store 40 ma i cc3 9 average v cc current at t rc = 200 ns, 3v, 25c typical 140 ma i cc4 average v cap current during autostore cycle 20 ma i sb v cc standby current 20 ma input leakage current (except hsb\) r 55 a input leakage current (for hsb\) r 400 10 a i oz off r state output leakage current r 10 10 a v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage v ss r 0.3 0.8 v v oh output high voltage 2.4 v v ol output low voltage 0.4 v v cap storage capacitor 80 180 f test conditions trc = 20 ns trc = 25 ns trc = 45 ns values obtained without output loads (iout = 0 ma) i cc1 average v cc current all inputs don?t care, v cc = max average current for duration t store between v cap pin and v ss , 6.3v rated all i/p cycling at cmos levels. values obtained without output loads (i out = 0 ma). all inputs don?t care, v cc = max average current for duration t store ce \ h (v cc ? 0.2v). all others v in g 0.2v or h (v cc ? 0.2v). standby current level after nonvolatile cycle is complete. inputs are static. f = 0 mhz. i ix 10 v cc = max, vss g vin g vcc v cc = max, vss g vin g vcc v cc = max, v ss g v out g v cc , ce\ or oe\ h v ih or we\ g v il i out = ?2 ma i out = 4 ma range ambient temperature vcc military r 55 o c to +125 o c 3.0v to 3.6v enhanced r 40 o c to +105 o c 3.0v to 3.6v industrial r 40 o c to +85 o c 3.0v to 3.6v
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 8 advance information data retention and endurance capacitance in the following table, the capacitance parameters are listed. 12 thermal resistance in the following table, the thermal resistance parameters are listed. 12 ac test loads 3.0v output 5 pf r1 r2 789 : 3.0v output 30 pf r1 r2 789 : for tri-state specs 577 : 577 : ac test conditions input pulse levels ....................................................0v to 3v input rise and fall times (10% - 90%)........................ <3 ns input and output timing reference levels .................... 1.5v note 12. these parameters are guaranteed by design but not tested. parameter description min unit data r data retention 20 years nv c nonvolatile store operation 200 cycles parameter description test conditions min unit c in input capacitance (addr, oe\, hsb\) x 450pf c in input capacitance (ce\ 1 r 4 , we\ 1 r 4 x 1 20 pf c out(dq) i/o capacitance x 125pf t a = 25c, f = 1 mhz, v cc = 0 to 3.0v parameter description test conditions 68 cqfp unit : jc thermal resistance (junction to case) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 11.3 o c/w
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 9 advance information ac switching characteristics switching waveforms sram read cycle #1: address controlled 13, 14, 17 address data output address valid previous data valid output data valid t rc t aa t oha notes 13.we\ must be high during sram read cycles. 14. device is continuously selected with ce\, oe\ low. 15.measured 200 mv from steady state output voltage. 16. if we\ is low when ce\ goes low, the outputs remain in the high impedance state. 17. hsb\ must remain high during read and write cycles. micross parameters alt parameters min max min max min max t ace t acs chip enable access time 20 25 45 ns t rc 13 t rc read cycle time 20 25 45 ns t aa 14 t aa address access time 20 25 45 ns t doe t oe output enable to data valid 10 12 20 ns t oha 14 t oh output hold after address change222ns t lzce 12, 15 t lz chip enable to output active222ns t hzce 12, 15 t hz chip disable to output active 8 10 15 ns t lzoe 12, 15 t olz output enable to output active000ns t hzoe 12, 15 t ohz output disable to output inactive 8 10 15 ns t pu 12 t pa chip enable to power active000ns t pd 12 t ps chip disable to power standby 20 25 45 ns t dbe r byte enable to data valid 10 12 20 ns t lzbe 12 r byte enable to output active000ns t hzbe 12 r byte disable to output inactive 8 10 15 ns t wc t wc write cycle time 20 25 45 ns t pwe t wp write pulse width 152030ns t sce t cw chip enable to end of write 15 20 30 ns t sd t dw data setup to end of write 8 10 15 ns t hd t dh data hold after end of write 0 0 0 ns t aw t aw address setup to end of write 15 20 30 ns t sa t as address setup to end of write 0 0 0 ns t ha t wr address hold after end of write 0 0 0 ns t hzwe 12, 15, 16 t wz write enable to output disable 8 10 15 ns t lzwe 12, 15 t ow output active after end of write222ns t bw r byte enable to end of write 15 20 30 ns sram read cycle sram write cycle parameters description 20 ns 25 ns 45 ns unit
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 10 advance information sram write cycle #1: we\ controlled 3, 16, 17,18 address valid address data output output data valid standby active high impedance ce oe bhe, ble i cc t hzce t rc t ace t aa t lzce t doe t lzoe t dbe t lzbe t pu t pd t hzbe t hzoe sram read cycle #2 ce and oe controlled 3, 13, 1 data output data input input data valid high impedance address valid address previous data t wc t sce t ha t bw t aw t pwe t sa t sd t hd t hzwe t lzwe we bhe, ble ce note 18. ce\ or we\ must be >v ih during address transitions.
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 11 advance information sram write cycle #2: ce\ controlled 3, 16, 17, 18 data output data input input data valid high impedance address valid address t wc t sd t hd bhe, ble we ce t sa t sce t ha t bw t pwe
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 12 advance information autostore/power up recall switching waveforms autostore or power up recall 22 notes 19. t hrecall starts from the time v cc rises above v switch. 20. if an sram write has not taken place since the last nonvolatile cycle, no autostore or hardware store takes place. 21. on a hardware store, software store / recall, autostore enable / disable and autostore initiation, sram operation continues to be enabled for time t delay . 22. read and write cycles are ignored during store, recall, and while vcc is below v switch. 23. hsb\ pin is driven high to vcc only by internal 100 kohm resistor, hsb\ driver is disabled. v switch v hdis v vccrise t store t store t hhhd t hhhd t delay t delay t lzhsb t lzhsb t hrecall t hrecall hsb out autostore power- up recall read & write inhibited ( rwi ) power-up recall read & write brown out autostore power-up recall read & write power down autostore note 20 note 20 note 23 min max min max min max t hrecall 19 power up recall duration 20 20 20 ms t store 20 store cycle duration 10 10 10 ms t delay 21 time allowed to complete sram cycle 202525ns v switch low voltage trigger level 2.65 2.65 2.65 v t vccrise 12 vcc rise time 150 150 150 s v hdis 12 hsb\ output driver disable voltage 1.9 1.9 1.9 v t lzhsb 12 hsb\ to output active time 555 s t hhhd 12 hsb\ high active time 500 500 500 ns unit parameters description 20 ns 25 ns 45 ns
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 13 advance information software controlled store/recall cycle in the following table, the software controlled store and recall cycle parameters are listed. 24, 25 switching waveforms ce\ and oe \controlled software store/recall cycle 26 autostore enable/disable cycle notes 24. the software sequence is clocked with ce\ controlled or oe\ controlled reads. 25. the six consecutive addresses must be read in the order listed in the mode selection table. we\ must be high during all six consecutive cycles. 26. dq output data at the sixth read may be invalid since the output is disabled at t delay time. min max min max min max t rc store/recall initiation cycle time 20 25 45 ns t sa address setup time 000ns t cw clock pulse width 152530ns t ha address hold time 000ns t recall recall duration 200 200 200 s unit parameters description 20 ns 25 ns 45 ns t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t store /t recall t hhhd t lzhsb high impedance address #1 address #6 address ce oe hsb(storeonly) dq (data) rwi t delay note 25 t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t delay address #1 address #6 address ce oe dq (data) t ss note 25 26
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 14 advance information hardware store cycle switching waveforms hardware store cycle 19 soft sequence processing 27, 28 min max min max min max t dhsb hsb\ to output active time when latch not set 20 25 25 ns t phsb hardware store pulse width 15 15 15 ns t 27, 28 soft sequence processing time 100 100 100 s unit parameters description 20 ns 25 ns 45 ns t ss , s o ft s equence p rocess i ng ti me 100 100 100 s t phsb t phsb t delay t dhsb t delay t store t hhhd t lzhsb write latch set write latch not set hsb (in) hsb (out) dq (data out) rwi hsb (in) hsb (out) rwi hsb pin is driven high to v cc only by internal sram is disabled as long as hsb (in) is driven low. hsb driver is disabled t dhsb 100kohm resistor, address #1 address #6 address #1 address #6 soft sequence command t ss t ss ce address v cc t sa t cw soft sequence command t cw notes 27. this is the amount of time it takes to take action on a soft sequence command. vcc power must remain high to effectively r egister command. 28. commands such as store and recall lock out i/o until operation is complete which further increases this time. see the spec i c command.
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 15 advance information truth table for sram operations hsb\ should remain high for sram operations. for x32 configuration ce\ 1 r 4 we\ 1 r 4 oe\ inputs / outputs mode power hxxhigh z deselect / power down standby l h l data out (dq0 r dq31) read active lhhhigh z output disabled active l l x data in (dq0 r dq31) write active
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 16 advance information micross package designator q ceramic 68 quad flat pack
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 17 advance information micross package designator qb ceramic 68 quad flat pack
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 18 advance information ordering information micross part number configuration package type speed (ns) process as8nvlc512k32qb r 20/mil 512k x 32 68 quad flat pack w/ tie r bar 20 mil as8nvlc512k32qb r 25/mil 512k x 32 68 quad flat pack w/ tie r bar 25 mil as8nvlc512k32qb r 45/mil 512k x 32 68 quad flat pack w/ tie r bar 45 mil as8nvlc512k32qb r 20/xt 512k x 32 68 quad flat pack w/ tie r bar 20 xt as8nvlc512k32qb r 25/xt 512k x 32 68 quad flat pack w/ tie r bar 25 xt as8nvlc512k32qb r 45/xt 512k x 32 68 quad flat pack w/ tie r bar 45 xt as8nvlc512k32qb r 20/et 512k x 32 68 quad flat pack w/ tie r bar 20 et as8nvlc512k32qb r 25/et 512k x 32 68 quad flat pack w/ tie r bar 25 et as8nvlc512k32qb r 45/et 512k x 32 68 quad flat pack w/ tie r bar 45 et as8nvlc512k32qb r 20/it 512k x 32 68 quad flat pack w/ tie r bar 20 it as8nvlc512k32qb r 25/it 512k x 32 68 quad flat pack w/ tie r bar 25 it as8nvlc512k32qb r 45/it 512k x 32 68 quad flat pack w/ tie r bar 45 it as8nvlc512k32q r 20/mil 512k x 32 68 quad flat pack 20 mil as8nvlc512k32q r 25/mil 512k x 32 68 quad flat pack 25 mil as8nvlc512k32q r 45/mil 512k x 32 68 quad flat pack 45 mil as8nvlc512k32q r 20/xt 512k x 32 68 quad flat pack 20 xt as8nvlc512k32q r 25/xt 512k x 32 68 quad flat pack 25 xt as8nvlc512k32q r 45/xt 512k x 32 68 quad flat pack 45 xt as8nvlc512k32q r 20/et 512k x 32 68 quad flat pack 20 et as8nvlc512k32q r 25/et 512k x 32 68 quad flat pack 25 et as8nvlc512k32q r 45/et 512k x 32 68 quad flat pack 45 et as8nvlc512k32q r 20/it 512k x 32 68 quad flat pack 20 it as8nvlc512k32q r 25/it 512k x 32 68 quad flat pack 25 it as8nvlc512k32q r 45/it 512k x 32 68 quad flat pack 45 it * available processes temperature it = industrial temperature range r 40 0 c to +85 0 c et = enhanced temperature range r 40 0 c to +105 0 c xt = military temperature range r 55 0 c to +125 0 c mil = military processing r 55 0 c to +125 0 c
nvsram as8nvlc512k32 as8nvlc512k32 rev. 0.5 04/10 micross components reserves the right to change products or speci cations without notice. 19 advance information document title 512k x 32 nvsram 3.3v high speed sram with non-volatile storage revision history rev # history release date status 0.0 document creation august 2009 advance 0.1 added micross information january 2010 advance 0.5 added q & qb package; changes to april 2010 advance pin description, dc electrical, capacitance, thermal resistance, autostore and order chart; updated diagrams on page 13, added diagrams and chart on page 14, added enhanced temp on page 1 & 18, changed cs\ to ce\ on pin assignment and pin out on page 1, added mil processing

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